1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to data processing systems including a plurality of processing circuits storing data values and having coherency control circuitry for controlling coherency of the data values stored within the plurality of control circuits.
2. Description of the Prior Art
It is known to provide data processing systems, such as the symmetric multiprocessing (SMP) systems designed by ARM Limited of Cambridge, England, which incorporate multiple processing circuits each storing data values (e.g. each having its own data cache) and coupled to coherency control circuitry for controlling the coherency of the data values stored within the different processing circuits. Such systems are useful in high performance computing environments and the coherency control circuitry permits data values to be shared between the different processing circuits without data coherence difficulties.
Within such systems the coherency control circuitry includes a TAG memory storing address values indicative of memory addresses associated with the data values stored within the different processing circuits. In this way, the coherency control circuitry is able to track which processing circuit is storing a copy of which data values. Accordingly, if one of the processing circuits modifies a data value stored locally and another processing circuit later wishes to access that data value, then it is possible for the modified data value to be forwarded to the requesting processing circuit such that it receives the most up-to-date value.
It can be important within data processing systems to provide a high degree of resilience to errors, such as hardware errors and soft errors (e.g. as produced by ionising radiation and the like). Such errors can corrupt the data values being stored and cause erroneous operation. If the data processing system is being used in a safety critical environment, such as a vehicle braking system, then it should include mechanisms to address such errors. One point of vulnerability in the high performance data processing systems described above is corruption of the data values stored within the TAG memory of the coherency control circuitry. This vulnerability may be addressed by associating error detection and correction codes with the address value stored within the TAG memory and providing error detecting and correcting circuitry to perform error detection and correction operations using those error detecting and correcting codes. However, a problem with this approach is that the requirement to store error correcting codes and the circuitry necessary to use those error correcting codes to correct address values represents a disadvantageous overhead both in terms of gate count and power consumption.